The pursuit of high-performance and energy-efficient computing for data-intensive algorithms such as deep neural networks (DNN) opens up exciting opportunities for emerging memories and unconventional architectures such as analog in-memory computing (IMC). To maximize the potential of such emerging computing technologies innovations across the stack (from devices to systems) are needed. In this talk, I will share some of our group’s recent efforts in exploiting spintronic components for developing efficient DNN hardware. First, a multi-level spintronic synaptic device based on a composite magnetic tunnel junction (MTJ) is proposed and analyzed in simulation. By integrating a standard MTJ free layer exchange coupled with a granular magnetic nanostructure, multiple near-continuous non-volatile resistive states can be induced thanks to the distribution of the energy barrier among individual magnetic grains. Our simulation demonstrated superior scalability and feasibility compared to other means of multi-level devices. Second, we propose to use stochastic MTJs for processing the array-level partial sums (PS) in crossbar architecture. Leveraging the probabilistic switching of spin-orbit torque (SOT) MTJs, the proposed PS processing eliminates the costly Analog-Digital Conversion in crossbar IMC, leading to significant improvement in energy and area efficiency. We further show that the accuracy loss due to quantization error can be mitigated by our novel PS-quantization-aware DNN training methodology. Our device-to-system co-optimization research demonstrates exciting opportunities for spintronics in developing next-generation intelligent computing systems.
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More information :https://www.spintec.fr/seminar-enabling-energy-efficient-artificial-intelligence-hardware-with-spintronics/​

Videoconference ​: https://univ-grenoble-alpes-fr.zoom.us/j/98769867024